1. Field of Invention
The present invention is related to audio amplifiers and in particular to increasing gain resolution of output stages of audio amplifiers.
2. Description of Related Art
Present day audio systems and integrated audio devices can have a plurality of sources that play into a plurality of different types of outputs, for example, an auxiliary input may be reproduced in an earphone amplifier or a DAC output may be played into an earpiece amplifier. In home high fidelity systems the selection is made by a switching device where the transition between sources is controlled so as not to introduce auditable effects of switching between input and output devices. In integrated audio devices a large number of distinct paths can be configured through summing amplifiers that perform a mixing operation. Unwanted sounds, e.g. pops and clicks, may be audible when the different source signals are at a different level when switched into the summing amplifier. A solution to the unwanted sounds could be to effectively mute the output, perform the required switching and then raise output amplitude back to where it was before muting.
The gain accuracy of audio amplifiers is usually determined by fixed value resistance in the feedback of the amplifier where the step size is dependent upon the number of elements in the feedback network and the intended range of the amplifier gain. If the gain is changed with a step size that is too large, for instance >0.01 dB for a 60 dB range, a zipping noise will be introduced. The large number of resistors needed to produce such an effect would make the amplifier device expensive and noncompetitive. Unwanted audio effects can often be eliminated by using discrete components on a PCB, but the cost of components can be in the order of magnitude of the integrated audio device itself.
US 2010/0166084 A1 (Galton et al.) is directed a successive re-quantizer that replaces a delta sigma modulator in a fractional-N PPL or DAC, which avoids spurious tone problems in non-linear analog circuitry. US 2006/0092059 A1 (Guimaraes) is directed to an automatic gain control using a sigma delta ADC. An amplifier is within a sigma delta time continuous loop prior to quantization and an attenuator in the feedback prior to summation with incoming signals. U.S. Pat. No. 7,821,341 B2 (Kim et al.) discloses a gain device with an amplifier that uses the gain device, which uses a linearly variable resistance to control the gain of the amplifier. In U.S. Pat. No. 7,583,213 B2 (Wang et al.) a signal processing system that is directed to changing the level of an input signal to produce an output signal, which includes a shifter, a sigma delta modulator and a level adjuster. U.S. Pat. No. 7,148,829 B2 (Inukai) is directed to a sigma delta modulation circuit having a gain control function, wherein a control unit controls the gain of a variable gain amplifier using a sigma delta modulator and a filter that operates on the output of the sigma delta modulator. In U.S. Pat. No. 7,102,441 B2 (Lee et al.) a variable gain amplifier circuit is directed to a use of a resistor ladder for obtaining a precise gain.
U.S. Pat. No. 6,404,367 B1 (Van der Zwan et al.) is directed to a sigma delta modulator that is used to interchange (chop) the input network and the feedback network to average out the differences in the two gain stages and produce a more accurate gain. U.S. Pat. No. 6,127,893 (Llewellyn et al.) is directed to a control circuit for controlling a level of an audio signal, wherein the control circuit is based on a R-2R resistive network having a plurality of resistor nodes and a plurality of switches to connect the resistors to a low impedance node. An article by Kevin. J Wang, “Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHZ Fractional-N PPL”, IEEE Journal of Solid State Circuits, Vol. 43, No. 12, December 2008, is directed to spurious tones in the output of a fractional-N PLL that are reduced by replacing a sigma delta modulator with a digital quantizer with a charge pump offset and a sampled loop filter. An article by James A. Kaehler, “Periodic-Switched Filter Networks—A means of Amplifying and Varying Transfer Functions”, IEEE Journal of Solid State Circuits, vol. sc-4, no. 4, August 1969, is directed to a technique of periodically switching filter networks to allows continuously variable filter parameters.
FIG. 1 shows a variable gain analog amplifier of prior art. An operational amplifier 10 is connected between an input signal, Vin, and an output signal, Vout, created by the operational amplifier. Switches S1 and S2 select the amount of negative feedback resistance connected between the output of the amplifier 10 and the negative input (summing junction) of the operational amplifier 10. The positive input terminal of the amplifier is connected to Vref, which is often ground potential. Selection of either switch S1 or S2 determines the amount of resistance between the input signal Vin and the negative input of the operational amplifier 10. Assuming that Rin=R1=R2, then the gain of the amplifier 10 is G1=−(R1+R2)/Rin=−2 when switch S1 is selected, and when switch S2 is selected the gain G2=−(R2)/(R1+Rin)=−½.
If the two switches S1 and S2 are toggled (turned on and off) at a relatively rapid rate with a fifty percent duty cycle, an average gain of Gavg=−(2+½)/2=−1.25 as shown in FIG. 2 where the two switches are opened and closed out of phase with each other. When Vin 20 applied to the amplifier is a ramp over a span of time t, Vout becomes a ramp 21 interrupted by the two different gains resulting from G1=−2 and G2=−½. The effective, or average output voltage 22 is twenty five percent higher than the input voltage Vin.
A portion of the control signal that drives the switches S1 and S2 can appear at the output of the amplifier, but this can be attenuated by the ratio of the switched resistance to the total resistance, or Rmod=Rsw/Rtot where Rmod is the control signal attenuation, Rsw is the switched resistance and Rtot=Rin+R1+R2. Also some of the high frequency switch control signal can be coupled to the output of the amplifier through parasitic capacitance of the circuitry. The higher the modulating frequency compared to the amplifier gain bandwidth (Fmod=fclk/fbw, where Fmod is the modulating frequency, fclk is the clock rate and fbw is the frequency bandwidth of the amplifier) and the lower Rmod, the lower the amplitude of the control signal that will appear at the output of the amplifier Vout.